The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which serves as a switch device.
A triac, for example, is enumerated for a semiconductor device affected by a gate trigger sensitivity problem. As is well known, the triac has two main electrodes and a single gate electrode which serves as a control gate. According to a combination of bias relations among the two main electrodes and the gate electrode, the triac is switched from an OFF state to an ON state, in one of four gate trigger modes.
A triac operating at the rated values of several hundreds volts or ten and several amperes receives, as a control signal, an output signal from an integrated circuit (IC) device. The output signal of the IC device is generally 10 mA or less. Thus, to drive the triac directly, the minimal value of a gate trigger current I.sub.GT capable of turning on the triac must be at least 10 mA for all of the four gate trigger modes. If the current value is insufficient to directly drive the triac, it is necessary to provide an amplifier made of a transistor, for example, between the IC device and the gate electrode of the triac.
To improve a gate trigger's sensitivity, the thickness of the semiconductor layer in contact with the gate electrode is reduced, which also serves to improve the carrier transmitting efficiency. Alternatively, two emitter regions formed on the major surfaces of a wafer may be so positioned as to partially overlap each other, to thereby allow injected carriers to operate effectively. If one of the above measures is taken, a decrease is allowed in the minimum value of the trigger current I.sub.GT capable of turning on the triac. In such a case, however, other characteristics, particularly critical off-voltage/unit of time (dv/dt).sub.s and critical off-voltage/unit of time (dv/dt).sub.c, at the time of commutation, are substantially damaged.
To solve this problem, the semiconductor device with the structure shown in FIGS. 1A to 1C and FIG. 2 has been proposed. As is well illustrated in FIGS. 1B and 1C, first to third semiconductor layers 1 to 3 of P, N and P conductivity types are superimposed one upon another. First and second emitter regions 4,5 of an N conductivity type, with predetermined patterns, are formed in the first and third semiconductor layers 1, 3, as shown. The third semiconductor layer 3 also has an auxiliary emitter region 9 formed thereon.
A first main electrode 6 is formed on the exposed major surface of the first semiconductor layer 1. The first main electrode 6 is in contact with the first semiconductor layer 1 and first emitter region 4. A second main electrode 7 is formed on the exposed major surface of the third semiconductor layer 3. The second main electrode 7 is in contact with the third semiconductor layer 3 and second emitter region 5. A gate electrode 8 is formed on the auxiliary emitter region 9. T1 and T2 designate main terminals, and G designates a gate terminal.
The first and second emitter regions 4, 5 are so patterned as to form therein a plurality of islands 10, 11 of the first and second semiconductor layers 1 and 3. Additionally, the first and second emitter regions 4, 5 overlap each other at portions 12 and 13, in the vicinity of the gate region or the gate electrode 8, as viewed in the laying direction of layers 1 to 3. As seen from FIG. 2, the number of islands 10, 11 per unit area in the overlapping portions 12, 13 is larger than that in the non-overlapping portions. For simplicity of illustration, the islands are omitted in the overlapping portions of FIGS. 1A to 1C. Further, in FIG. 1A, the main electrodes 6, 7 are omitted, for the same reason.
In the semiconductor device thus arranged, the presence of the overlapping portions 12, 13 of the first and second emitter regions 4, 5 provides satisfactorily high gate trigger sensitivity. Furthermore, the high density of the islands in the overlapping portions substantially increases the critical off-voltage/unit of time (dv/dt).sub.c at the time of commutation.
The gate trigger characteristics of the four semiconductor devices arranged as shown in FIGS. 1A-1C and FIG. 2 are illustrated in FIGS. 3A to 3D. When those characteristics are obtained the polarity at terminal G is set relative to the polarity at terminal T1. The critical off-voltage/unit of time (dv/dt).sub.c at the time of commutation in modes I and III and the critical current/unit of time (di/dt) in mode I are as shown in FIGS. 4A to 4C. As may be seen from those figures, the critical off-voltage/unit of time (dv/dt).sub.c at the time of commutation in modes I and III is good. When this device is turned off in mode I, T1: (-) and T2: (+), as shown in FIG. 4C, the critical current/unit of time (di/dv) is from approximately 30 to 50 A/.mu.s, which is very poor. The presumed reason for this is that, when a sharply rising current is caused to flow in the above bias mode, it is hard for the device to turn off in the vicinity of the gate region.
Ideally, in the semiconductor device serving as a switch device, the characteristics (dv/dt).sub.c at the time of commutation in modes I and III and the characteristic (di/dt) in mode I should all be satisfactory.